Digital Design Intern
System-on-Chip Lab, NUST
Rawalpindi, Pakistan
June 2025 – Aug 2025
Role Summary
- Designed and tested FPGA modules on Intel DE1-SoC using Verilog.
- Implemented VGA visualization algorithms by integrating FSMs with datapath modules.
- Completed 9 FPGA labs covering dual-port RAM, VGA controllers, and processor interfacing.
- Applied ETH Zurich Computer Architecture concepts to hardware design projects.
Role Summary
- Designed and tested FPGA modules on Intel DE1-SoC using Verilog.
- Implemented VGA visualization algorithms by integrating FSMs with datapath modules.
- Completed 9 FPGA labs covering dual-port RAM, VGA controllers, and processor interfacing.
- Applied ETH Zurich Computer Architecture concepts to hardware design projects.